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| TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Rev. 02 -- 03 July 2002 Product data 1. Description The TDA8768AH is a biCMOS 12-bit Analog-to-Digital Converter (ADC) optimized for GSM and EDGE cellular infrastructures, professional telecommunications and imaging, and advanced FM radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features s s s s s s s s s s s s s s s s 12-bit resolution Sampling rate up to 70 MHz -3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or twos complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible static digital inputs TTL and CMOS compatible digital outputs Differential AC or PECL clock input; TTL compatible Power dissipation 550 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample-and-hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included -40 C to +85 C ambient temperature. 3. Applications s High-speed analog-to-digital conversion for: x Cellular infrastructure (GSM and EDGE) x Professional telecommunication x Advanced FM radio x Radar x Imaging (camera scanner) x Set Top Box (STB) x Medical imaging. Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 4. Quick reference data Table 1: Symbol VCCA VCCD VCCO ICCA ICCD ICCO INL DNL fCLK(max) Quick reference data Parameter analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity differential non-linearity (no missing code) maximum clock frequency TDA8768AH/4 TDA8768AH/5 TDA8768AH/7 Ptot total power dissipation fCLK = 55 MHz fi = 20 MHz fCLK = 20 MHz fi = 400 kHz fCLK = 20 MHz fi = 400 kHz fCLK = 20 MHz fi = 400 kHz Conditions Min 4.75 4.75 3.0 40 55 70 550 Typ 5.0 5.0 3.3 78 27 3 2.6 0.5 Max 5.25 5.25 3.6 87 30 4 4.5 +1.1 - 0.95 660 Unit V V V mA mA mA LSB LSB MHz MHz MHz mW 5. Ordering information Table 2: Ordering information Package Name TDA8768AH/4 TDA8768AH/5 TDA8768AH/7 QFP44 Description plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm Version Sampling frequency (MHz) 55 70 Type number SOT307-2 40 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 2 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 6. Block diagram VCCA1 2 n.c. FSref Vref 6 to 10, 13, 14, 16 12 11 VREF REFERENCE CLOCK DRIVER VCCA3 VCCA4 3 41 CLK 35 CLK 36 VCCD1 VCCD2 37 15 OTC 18 CE 19 21 D11 MSB 22 D10 23 D9 24 D8 25 D7 AMP CMOS OUTPUTS VI VI 43 42 sampleand-hold ANALOG-TO-DIGITAL CONVERTER LATCHES 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 SH 39 32 D0 33 LSB VCCO data outputs TDA8768A CMADC DEC 1 5 CMADC REFERENCE OVERFLOW/ UNDERFLOW LATCH CMOS OUTPUT 20 IR 44 4 40 38 17 34 005aaa024 AGND1 AGND3 AGND4 DGND1 DGND2 OGND Fig 1. Block diagram. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 3 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 7. Pinning information 7.1 Pinning 38 DGND1 44 AGND1 40 AGND4 37 VCCD1 41 VCCA4 34 OGND 36 CLK 35 CLK 39 SH 43 VI 42 VI CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 33 VCCO 32 D0 31 D1 30 D2 29 D3 TDA8768AH 28 D4 27 D5 26 D6 25 D7 24 D8 23 D9 n.c. 10 Vref 11 FSref 12 n.c. 13 n.c. 14 VCCD2 15 n.c. 16 DGND2 17 OTC 18 CE 19 IR 20 D11 21 D10 22 FCE002 Fig 2. Pin configuration. 7.2 Pin description Table 3: Symbol CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c. n.c. VREF FSREF 9397 750 09656 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 Description regulator output common mode ADC input analog supply voltage 1 (+5 V) analog supply voltage 3 (+5 V) analog ground 3 decoupling node not connected not connected not connected not connected not connected reference voltage input full-scale reference output (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 4 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Pin description...continued Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Description not connected not connected digital supply voltage 2 (+5 V) not connected digital ground 2 control input twos complement output; active HIGH chip enable input (CMOS level; active LOW) in-range output data output; bit 11 (MSB) data output; bit 10 data output; bit 9 data output; bit 8 data output; bit 7 data output; bit 6 data output; bit 5 data output; bit 4 data output; bit 3 data output; bit 2 data output; bit 1 data output; bit 0 (LSB) output supply voltage (+3.3 V) output ground complementary clock input clock input digital supply voltage 1 (+5 V) digital ground 1 sample-and-hold enable input (CMOS level; active HIGH) analog ground 4 analog supply voltage 4 (+5 V) analog input voltage complementary analog input voltage analog ground 1 Table 3: Symbol n.c. n.c. VCCD2 n.c. DGND2 OTC CE IR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCCO OGND CLK CLK VCCD1 DGND1 SH AGND4 VCCA4 VI VI AGND1 8. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO 9397 750 09656 Parameter analog supply voltage digital supply voltage output supply voltage Conditions [1] [1] [1] Min -0.3 -0.3 -0.3 Max +7.0 +7.0 +7.0 Unit V V V (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 5 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 4: Limiting values...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Parameter supply voltage difference VCCA - VCCD VCCD - VCCO VCCA - VCCO VI, VI VCLK(p-p) input voltage at pins 42 and 43 input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) output current storage temperature ambient temperature junction temperature referenced to AGND -1.0 -1.0 -1.0 0.3 +1.0 +4.0 +4.0 VCCA VCCD V V V V V Conditions Min Max Unit IO Tstg Tamb Tj [1] -55 -40 - 10 +150 +85 150 mA C C C The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 V and +7.0 V provided that the supply voltage differences VCC are respected. 9. Thermal characteristics Table 5: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Condition in free air Value 75 Unit K/W 10. Characteristics Table 6: Characteristics VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = -40 to 85 C; VI(p-p) - VI(p-p) = 1.9 V; Vref = VCCA3-1.75 V; VI(CM) = VCCA3-1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Supplies VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current fCLK = 20 MHz; fi = 400 kHz fCLK = 55 MHz; fi = 20 MHz Inputs 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Parameter Conditions Test [1] Min 4.75 4.75 3.0 Typ 5.0 5.0 3.3 78 27 3 6.2 9.5 Max 5.25 5.25 3.6 87 30 4 9 12 Unit V V V mA mA mA mA mA I I I I fCLK = 40 MHz; fi = 4.43 MHz C - Product data Rev. 02 -- 03 July 2002 6 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = -40 to 85 C; VI(p-p) - VI(p-p) = 1.9 V; Vref = VCCA3-1.75 V; VI(CM) = VCCA3-1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol VIL VIH IIL IIH VCLK(p-p) Parameter DGND)[2] PECL mode; VCCD = 5 V TTL mode HIGH-level input voltage LOW-level input current HIGH-level input current differential AC input voltage for switching (VCLK(p-p) - VCLK(p-p)) input resistance input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input current HIGH-level input current input resistance input capacitance common mode input voltage VIL = 0.8 V VIH = 2.0 V SH = HIGH SH = HIGH fi = 20 MHz fi = 20 MHz VI = VI; output code 2047 PECL mode; VCCD = 5 V TTL mode VCLK or VCLK = 3.19 V VCLK or VCLK = 3.83 V I C I C C C 3.19 0 3.83 2.0 -10 1 1.5 3.52 0.8 4.12 VCCD 10 2.0 V V V V A A V LOW-level input voltage Conditions Test [1] Min Typ Max Unit CLK and CLK (referenced to AC driving mode; DC voltage C level = 2.5 V fCLK = 55 MHz fCLK = 55 MHz D D I I I I C C D D C Ri Ci VIL VIH IIL IIH IIL IIH Ri Ci VI(CM) 2 0 2.0 -20 - 10 10 14 450 2 0.8 VCCD 20 - k pF V V A A A A M fF OTC, SH and CE (referenced to DGND); see Tables 7 and 8 VI and VI (referenced to AGND); see Table 7, Vref = VCCA3 - 1.75 V VCCA3 VCCA3 - 1.6 VCCA3 V - 1.7 - 1.2 VCCA3 - 1.6 1 VCCA3 - 1.75 0.3 1.9 2 10 V mA V A V Voltage controlled regulator output CMADC Vo(CM) IL Vref Iref common mode output voltage load current [3] I I fi = 20 MHz; fCLK = 55 Msps C C Vref = VCCA3 - 1.75 V VI(CM) = VCCA3 - 1.6 V C Voltage input Vref full-scale fixed voltage input current at Vref VI(p-p) - VI(p-p) input voltage amplitude (peak-to-peak value) Voltage controlled regulator output FSref Vo(ref) 1.9 V full-scale output voltage I - VCCA3 - 1.75 - V Outputs (referenced to OGND) Digital outputs D11 to D0 and IR (referenced to OGND) VOL 9397 750 09656 LOW-level output voltage IOL = 2 mA I 0 - 0.5 V (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 7 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = -40 to 85 C; VI(p-p) - VI(p-p) = 1.9 V; Vref = VCCA3-1.75 V; VI(CM) = VCCA3-1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol VOH Io Parameter HIGH-level output voltage output current in 3-state Conditions IOH = - 0.4 mA output level between 0.5 V and VCCO Test [1] I I Min VCCO - 0.5 -20 Typ Max VCCO +20 Unit V A Switching characteristics Clock frequency fCLK; see Figure 3 fCLK(min) fCLK(max) minimum clock frequency maximum clock frequency TDA8768AH/4 TDA8768AH/5 TDA8768AH/7 tCLKH tCLKL Linearity INL DNL integral non-linearity differential non-linearity fCLK = 20 MHz; fi = 400 kHz fCLK = 20 MHz; fi = 400 kHz (no missing code guaranteed) VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C; output code = 2047 VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C -3 dB; full-scale input fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz second harmonic TDA8768AH/5 (fCLK = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz second harmonic TDA8768AH/7 (fCLK = 70 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz I I 2.6 0.5 4.5 LSB +1.1 LSB - 0.95 25 mV clock pulse width HIGH clock pulse width LOW fi = 20 MHz fi = 20 MHz C I C C C 40 55 70 6.8 6.8 MHz MHz MHz ns ns SH = HIGH C 7 MHz Analog signal processing; 50% clock duty factor; VI - VI = 1.9 V; Vref = VCCA3 - 1.75 V; see Table 7 Oerr offset error C -25 5 EG gain error amplitude; spread from device to device analog bandwidth second harmonic TDA8768AH/4 (fCLK = 40 MHz) C -7 - +7 %FS Bandwidth (fCLK = 55 MHz) [4] B Harmonics H2 C C C C C C C I C C C -78 -77 -74 -71 -77 -77 -76 - 73 -76 -74 -70 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS C 220 245 MHz 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 8 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = -40 to 85 C; VI(p-p) - VI(p-p) = 1.9 V; Vref = VCCA3-1.75 V; VI(CM) = VCCA3-1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol H3 Parameter third harmonic TDA8768AH/4 (fCLK = 40 MHz) Conditions fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz third harmonic TDA8768AH/5 (fCLK = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz third harmonic TDA8768AH/7 (fCLK = 70 MHz) Total harmonic THD distortion[5] total harmonic distortion TDA8768AH/4 (fCLK = 40 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz total harmonic distortion TDA8768AH/5 (fCLK = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz total harmonic distortion TDA8768AH/7 (fCLK = 70 MHz) Thermal noise (fCLK = 55 MHz) Nth(rms) thermal noise (RMS value) shorted input; SH = HIGH; fCLK = 55 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz signal-to-noise ratio TDA8768AH/5 (fCLK = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz signal-to-noise ratio TDA8768AH/7 (fCLK = 70 MHz) 9397 750 09656 Test [1] C C C C C C C I C C C C C C C C C C I C C C C Min - Typ -74 -74 -74 -73 -74 -74 -74 -72 -74 -74 -73 -68 -68 -68 -68 -68 -68 -68 -68 -68 -67 -67 0.45 Max - Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS LSB fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Signal-to-noise ratio [6] SNR signal-to-noise ratio TDA8768AH/4 (fCLK = 40 MHz) C C C C C C C I C C C 64 64 64 64 64 64 64 64 64 64 63 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS fi = 4.43 MHz fi = 10 MHz fi = 15 MHz (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 9 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = -40 to 85 C; VI(p-p) - VI(p-p) = 1.9 V; Vref = VCCA3-1.75 V; VI(CM) = VCCA3-1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol SFDR Parameter spurious free dynamic range TDA8768AH/4 (fCLK = 40 MHz) Conditions fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz spurious free dynamic range TDA8768AH/5 (fCLK = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz spurious free dynamic range TDA8768AH/7 (fCLK = 70 MHz) Effective number of bits ENOB [7] Test [1] C C C C C C C I C C C C C C C C C C I C C C C C Min - Typ 72 71 71 69 72 71 71 69 70 69 69 10.1 10.1 10.1 10 10.1 10.1 10 10 10 10 10 -68 -70 Max - Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS bits bits bits bits bits bits bits bits bits bits bits dB dB Spurious free dynamic range; see Figure 7, 13 and 14 fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz effective number of bits TDA8768AH/4 (fCLK = 40 MHz) effective number of bits TDA8768AH/5 (fCLK = 55 MHz) effective number of bits TDA8768AH/7 (fCLK = 70 MHz) Intermodulation; (fCLK = 55 MHz; fi = 20 TTIR d3 two-tone intermodulation rejection third-order intermodulation distortion bit error rate MHz)[8] Bit error rate (fCLK = 55 MHz) BER fi = 20 MHz; VI = 16 LSB at C code 2047 C C C 10-14 times/ sample ns ns ns Timing (CL = 10 pF)[9] td(s) th(o) td(o) sampling delay time output hold time output delay time 4 0.25 6.4 9.0 1 13 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 10 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = -40 to 85 C; VI(p-p) - VI(p-p) = 1.9 V; Vref = VCCA3-1.75 V; VI(CM) = VCCA3-1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol tdZH tdZL tdHZ tdLZ [1] [2] Parameter enable HIGH enable LOW disable HIGH disable LOW Conditions Test [1] C C C C Min - Typ 5.1 7.0 9.7 9.5 Max 9.0 11 14 13 Unit ns ns ns ns 3-state output delay times; see Figure 4 [3] [4] [5] D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested. The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLK inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLK pin has to be connected to the ground. The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA; see Figure 12. The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics: 2 2 2 2 2 ( 2nd ) + ( 3rd ) + ( 4th ) + ( 5th ) + ( 6th ) THD = 20 log ------------------------------------------------------------------------------------------------------------------------------------2 F [6] [7] [8] [9] where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. Signal-to-noise ratio (SNR) takes into account all harmonics above five and noise up to nyquist frequency; see Figure 8. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB x 6.02 + 1.76 dB; see Figure 5. Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (-6 dB below full scale for each input signal). d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. Output data acquisition: the output data is available after the maximum delay of td; see Figure 3. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 11 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Output coding with differential inputs (typical values to AGND); Vi(p-p) - Vi(p-p) = 1.9 V, Vref = VCCA3 - 1.75 V Vi(p-p) Vi(p-p) IR Binary outputs D11 to D0 Twos complement outputs[1] D11 to D0 100000000000 1 0 0 0 0 0 0 0 0 0 00 100000000001 111111111111 011111111110 011111111111 011111111111 Table 7: Code Underflow 0 1 2047 4094 4095 Overflow [1] <3.125 3.125 - - 3.6 - - 4.075 >4.075 >4.075 4.075 - - 3.6 - - 3.125 <3.125 0 1 1 1 1 1 0 000000000000 000000000000 000000000001 011111111111 111111111110 111111111111 111111111111 Twos complement reference is inverted MSB. Table 8: OTC 0 1 X[1] [1] Mode selection CE 0 0 1 D0 to D11 and IR binary; active twos complement; active high-impedance X = don't care. Table 9: SH 1 0 Sample-and-hold selection Sample-and-hold active inactive; tracking mode tCLKH tCLKL HIGH CLK 50 % LOW sample N sample N + 1 sample N + 2 Vl t ds DATA D0 to D11 DATA N-2 DATA N-1 td th HIGH DATA N DATA N+1 MBG855 50 % LOW Fig 3. Timing diagram. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 12 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) V CCD CE 0V tdHZ HIGH 90 % output data tdLZ HIGH output data LOW 10 % TEST V CCO 3.3 k TDA8768A 15 pF CE S1 t dLZ t dZL t dHZ t dZH S1 VCCO VCCO OGND OGND MBG856 50 % tdZH 50 % tdZL LOW 50 % fCE = 100 kHz. Fig 4. Timing diagram and test conditions of 3-state output delay time. 10.4 ENOB (bits) 10.2 10 (3) 9.8 9.6 (1) (2) 005aaa011 THD (dBFS) -60 -62 -64 -66 (3) -68 -70 -72 -58 005aaa012 9.4 9.2 9 (2) (1) 1 10 fi (MHz) 100 1 10 fi (MHz) 100 (1) 40 Msps (2) 55 Msps (3) 70 Msps (1) 40 Msps (2) 55 Msps (3) 70 Msps Fig 5. Effective number of bits (ENOB) as a function of input frequency (sample device). Fig 6. Total harmonic distortion (THD) as a function of input frequency (sample device). 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 13 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 74 SFDR (dBFS) 72 70 68 66 (1) 005aaa013 65.5 SNR (dBFS) 65 (3) (1) 64.5 005aaa014 (3) (2) 64 63.5 63 62.5 (2) 64 62 60 1 10 fi (MHz) 100 62 1 10 fi (MHz) 100 (1) 40 Msps (2) 55 Msps (3) 70 Msps (1) 40 Msps (2) 55 Msps (3) 70 Msps Fig 7. Spurious free dynamic range (SFDR) as a function of input frequency (sample device). Fig 8. Signal-to-noise ratio (SNR) as a function of input frequency (sample device). 0 power spectrum (dB) -20 005aaa015 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 measured output range (MHz) Fig 9. Single-tone; fi = 20 MHz; fCLK = 55 Msps. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 14 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 0 power spectrum (dB) -20 005aaa016 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 measured output range (MHz) Fig 10. Two-tone; fi1 = 20 MHz; fi2 = 20.1 MHz; fCLK = 55 Msps. 2 005aaa017 1.5 output range (INL) 1 0.5 0 -0.5 -1 -1.5 -2 0 512 1024 1536 2048 2560 3072 3584 4096 output code Fig 11. Integral non-linearity (INL). 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 15 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 005aaa018 0.6 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 output code Fig 12. Differential non-linearity (DNL). 80 SFDR (dBFS) 70 005aaa019 60 50 (1) 40 (2) 30 (3) 20 -60 -50 -40 -30 -20 -10 Vi (dBFS) 0 (1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB Fig 13. SFDR as a function of input amplitude; FS = 1.9 V; fCLK = 40 MHz. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 16 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 80 SFDR (dBFS) 70 005aaa020 60 50 (2) 40 (1) 30 (3) 20 -60 -50 -40 -30 -20 -10 Vi (dBFS) 0 (1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB Fig 14. Spurious free dynamic range (SFDR) as a function of input amplitude; FSREF = 1.9 V; fCLK = 55 MHz. 72 (3) 005aaa021 11 2.6 2.4 (Vi - Vi)(p-p) (V) 2.2 2 005aaa022 70 (dB) 68 10.5 bits (2) 10 66 9.5 1.8 1.6 1.4 64 (1) 62 9 8.5 1.2 60 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 Vref (V) 8 1 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 VCCA - Vref (V) (1) = SNR (2) = ENOB (3) = SFDR Fig 15. ENOB, SFDR and SNR as a function of Vref; fCLK = 55 MHz; fi = 4.43 MHz. Fig 16. ADC full-scale; VI(p-p) - VI(p-p) as a function of VCCA - Vref. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 17 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 11. Application information 11.1 Application diagrams 5V 100 nF 220 nF 1:1 100 100 VI 1 5V 10 nF 100 nF 2 3 4 5 100 nF n.c. n.c. n.c. n.c. n.c. Vref 6 7 8 9 10 11 VI SH mode 5V 100 nF CLK 5V 44 43 42 41 40 39 38 37 36 35 34 100 nF 33 32 31 30 29 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 TDA8768A 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 n.c. 5V 100 nF n.c. n.c. IR D10 D11 (MSB) chip select input output format select FCE003 The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram. TTL input D MC100 ELT20 PECL CLK TDA8768A CLK 270 270 FCE168 Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 18 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) CLK TDA8768A TTL input CLK FCE169 Fig 19. Application diagram for TTL single-ended clock. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 19 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 11.2 Demonstration board B11 CLK2 J2 R4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 50 VCC C6 330 nF C15 10 nF VCCO FL3 C13 100 nF 34 35 CLK C19 S5 VCCA C17 10 nF 36 OGND CLK VCCO 33 32 DO 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7 24 D8 23 D9 CLK1 J3 R3 50 10 nF VCCD D10 D11 IR CE 22 21 20 19 18 17 16 C12 100 nF S3 FL2 C18 10 nF FL1 C5 330 nF VCC B5 S4 IN J1 C9 220 nF R1 100 TR1 CMADC R9 100 MCLT1_6T_KK81 CMADC AGDN3 VCCA1 VCCA3 DEC 1 2 9 10 5 3 4 6 7 8 C8 330 nF S1 VCCA P1 5 k C14 100 nF FL4 C16 10 nF VCC C7 330 nF C10 100 nF C11 100 nF B7 P2 11 n.c. Vref CLK 37 V CCD1 38 DGND1 39 SH 40 AGND4 41 V CCA4 42 V i 43 V i 44 AGND1 IC2 TDA8768A OTC DGND2 n.c n.c. n.c. n.c. n.c. VCCD2 15 14 n.c 13 n.c 12 FSref S2 R7 VCCA VCCA 1 k 1.2 k R6 2.4 k BYD17G D3 12 V GND J4 2 J4 1 IC1 1 C1 22 F (20 V) IN OUT 3 C2 4.7 F (16 V) VCC TM3 R2 82 VCC MC78MO5CDT GND PMBT 2222A T1 VCCO R8 750 D1 LGT679 BZV55C3V6 C3 1 F D2 R5 4.7 k C4 1 F TP2 VCCO FCE733 C8 = close to TR1 pin. Fig 20. Demonstration board schematic. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 20 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) R1 J1 C9 TR1 B4 1 TM2 J3 1 S5 S1 P1 R9 C7 FL4 C10 B7 C11 R6 P2 S2 R7 TM1 S3 S4 FL2 J2 C5 B5 C14 1 12 1 R3 34 IC2 23 IC1 TM3 R8 R2 T1 R5 C12 1 C1 C2 D3 J4 1 2 B8 TP2 C4 D1 C3 D2 R4 B11 1 F68A21 MSD808 Fig 21. Component placement (top side). C6 FL3 C8 C19 C15 C13 C16 C17 FL1 C18 F68A22 MSD809 Fig 22. Component placement (underside). 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 21 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) FCE725 Fig 23. PCB layout (top layer). FCE726 Fig 24. PCB layout (ground layer). 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 22 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) FCE727 Fig 25. PCB layout (power plane). 12. Support information 12.1 Definitions 12.1.1 Non-linearities Integral Non-Linearity (INL).: It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V in ( i ) - V in ( ideal ) INL ( i ) = ----------------------------------------------S where i = 0 ( 2 - 1 ) and S = slope of the ideal straight line = code width; i = code value. Differential Non-Linearity (DNL).: It is the deviation in code width from the value of 1LSB. V in ( i + 1 ) - V in ( i ) DNL ( i ) = -------------------------------------------- - 1 S where i = 0 (2 - 2) n n 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 23 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 12.1.2 Dynamic parameters (single tone) Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft/fs = M/N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. FCE710 magnitude a1 SFDR s a2 a3 ak measured output range fs/2 Fig 26. Spectrum of full-scale input sine wave with frequency ft. Remark: in the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and "quantization noise". Signal-to-noise and distortion (SINAD): The ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ db ] = 10 log ----------------------------------------P noise + distortion Effective Number of Bits (ENOB): It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: ENOB = ( SINAD [ dB ] - ( 1 76 ) ) ( 6 02 ) Total Harmonic Distortion (THD): The ratio of the power of the harmonics to the power of the fundamental. For k-1 harmonics the THD is: P harmonics THD [ dB ] = 10 log -------------------------P signal where P harmonics = a 2 + a 3 + a P signal = a 2 1 2 2 2 k The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 24 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Signal-to-Noise Ratio (SNR): The ratio of the output signal power to the noise power, excluding the harmonics and the DC component. P signal SNR [ dB ] = 10 log ---------------P noise Spurious Free Dynamic Range (SFDR): The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic, excluding DC component. a1 SFDR [ dB ] = 20 log ----------------max ( s ) 12.1.3 Intermodulation distortion Spectral analysis (dual-tone) 0 005aaa023 -20 (dB) -40 IMD3 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 measured output range (MHz) Fig 27. Spectral analysis (dual-tone) From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd-order components) are defined, as follows. IMD2 (IMD3): The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 25 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) The total intermodulation distortion IMD is given by P intermod IMD [ dB ] = 10 log ----------------------P signal where, P intermod = a +a 2 (f im t1 2 (f im t1 - f t2 ) - a 2 ( 2 f t1 im 2 (f im t1 + f t2 ) + a 2 ( 2 f t1 im 2 (f im t1 - 2 f t2 ) + 2 f t2 ) + a - f t2 ) + a + f t2 ) P signal = a 2 ( f t1 ) + a 2 ( f t2 ) and a 2 (f ) im t is the power in the intermodulation component at frequency ft. 12.1.4 Noise Power Ratio (NPR) When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 26 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 13. Package outline QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 34 23 22 ZE e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L A1 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 Fig 28. SOT307-2. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 27 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 15. Soldering 15.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 28 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 15.5 Package related soldering information Table 10: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO [1] [2] Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] suitable not recommended[4][5] not recommended[6] Reflow[2] suitable suitable suitable suitable suitable [3] [4] [5] [6] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 29 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 16. Revision history Table 11: Rev Date 02 20020703 Revision history CPCN Description Product data (9397 750 09656); supersedes Preliminary specification TDA8768A_1 of 20020409 (9397 750 08323) Modifications: * * * 01 20020409 - Raise to Product Features list corrected Change value of INL in Table 6. Preliminary data; initial version. 9397 750 09656 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 30 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 17. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 18. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 09656 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 02 -- 03 July 2002 31 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 12 12.1 12.1.1 12.1.2 12.1.3 12.1.4 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . 18 Application diagrams . . . . . . . . . . . . . . . . . . . 18 Demonstration board . . . . . . . . . . . . . . . . . . . 20 Support information . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 23 Dynamic parameters (single tone) . . . . . . . . . 24 Intermodulation distortion . . . . . . . . . . . . . . . . 25 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . . 26 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27 Handling information. . . . . . . . . . . . . . . . . . . . 28 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29 Package related soldering information . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 03 July 2002 Document order number: 9397 750 09656 |
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